module alu ( op, a, b, out );
	input wire [2:0] op;
	input wire [7:0] a;
	input wire [7:0] b;

	output wire [7:0] out;

	wire [7:0] andresult;
	assign andresult = a&b;
	wire [7:0] orresult;
	assign orresult = a|b;
	wire [7:0] xorresult;
	assign xorresult = a^b;
	wire [7:0] addresult;
	assign addresult = a+b;
	wire [7:0] subresult;
	assign subresult = a-b;

	assign out = op[2] ? 
		( op[1] ? 8'h0 : (op[0] ? subresult : addresult )) :
		( op[1] ? (op[0] ? xorresult : orresult ) : (op[0] ? andresult : a ));

endmodule