// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Model implementation (design independent parts)

#include "Vcomputer__pch.h"

//============================================================
// Constructors

Vcomputer::Vcomputer(VerilatedContext* _vcontextp__, const char* _vcname__)
    : VerilatedModel{*_vcontextp__}
    , vlSymsp{new Vcomputer__Syms(contextp(), _vcname__, this)}
    , clk{vlSymsp->TOP.clk}
    , videoSignal{vlSymsp->TOP.videoSignal}
    , reset{vlSymsp->TOP.reset}
    , ACC{vlSymsp->TOP.ACC}
    , PC{vlSymsp->TOP.PC}
    , rootp{&(vlSymsp->TOP)}
{
    // Register model with the context
    contextp()->addModel(this);
}

Vcomputer::Vcomputer(const char* _vcname__)
    : Vcomputer(Verilated::threadContextp(), _vcname__)
{
}

//============================================================
// Destructor

Vcomputer::~Vcomputer() {
    delete vlSymsp;
}

//============================================================
// Evaluation function

#ifdef VL_DEBUG
void Vcomputer___024root___eval_debug_assertions(Vcomputer___024root* vlSelf);
#endif  // VL_DEBUG
void Vcomputer___024root___eval_static(Vcomputer___024root* vlSelf);
void Vcomputer___024root___eval_initial(Vcomputer___024root* vlSelf);
void Vcomputer___024root___eval_settle(Vcomputer___024root* vlSelf);
void Vcomputer___024root___eval(Vcomputer___024root* vlSelf);

void Vcomputer::eval_step() {
    VL_DEBUG_IF(VL_DBG_MSGF("+++++TOP Evaluate Vcomputer::eval_step\n"); );
#ifdef VL_DEBUG
    // Debug assertions
    Vcomputer___024root___eval_debug_assertions(&(vlSymsp->TOP));
#endif  // VL_DEBUG
    vlSymsp->__Vm_deleter.deleteAll();
    if (VL_UNLIKELY(!vlSymsp->__Vm_didInit)) {
        vlSymsp->__Vm_didInit = true;
        VL_DEBUG_IF(VL_DBG_MSGF("+ Initial\n"););
        Vcomputer___024root___eval_static(&(vlSymsp->TOP));
        Vcomputer___024root___eval_initial(&(vlSymsp->TOP));
        Vcomputer___024root___eval_settle(&(vlSymsp->TOP));
    }
    VL_DEBUG_IF(VL_DBG_MSGF("+ Eval\n"););
    Vcomputer___024root___eval(&(vlSymsp->TOP));
    // Evaluate cleanup
    Verilated::endOfEval(vlSymsp->__Vm_evalMsgQp);
}

//============================================================
// Events and timing
bool Vcomputer::eventsPending() { return false; }

uint64_t Vcomputer::nextTimeSlot() {
    VL_FATAL_MT(__FILE__, __LINE__, "", "%Error: No delays in the design");
    return 0;
}

//============================================================
// Utilities

const char* Vcomputer::name() const {
    return vlSymsp->name();
}

//============================================================
// Invoke final blocks

void Vcomputer___024root___eval_final(Vcomputer___024root* vlSelf);

VL_ATTR_COLD void Vcomputer::final() {
    Vcomputer___024root___eval_final(&(vlSymsp->TOP));
}

//============================================================
// Implementations of abstract methods from VerilatedModel

const char* Vcomputer::hierName() const { return vlSymsp->name(); }
const char* Vcomputer::modelName() const { return "Vcomputer"; }
unsigned Vcomputer::threads() const { return 1; }
void Vcomputer::prepareClone() const { contextp()->prepareClone(); }
void Vcomputer::atClone() const {
    contextp()->threadPoolpOnClone();
}