module memoryandvideo(clk, address,store,dataIn, dataOut,videoSignal);

  input clk;
  input [15:0] address;
  input store;
  input [7:0] dataIn;
  output [7:0] dataOut;
  assign dataOut = RAM[address];
  output videoSignal;
  assign videoSignal = RAM[{13'h0,pixelCounter[5:3]}][pixelCounter[2:0]];

  reg [5:0] pixelCounter;

  always @(posedge clk)
	  pixelCounter <= pixelCounter+1;
  
  always @(posedge clk)
    if(store)
      RAM[address]<=dataIn;
    
  initial 
    RAM = '{(1<<16){8'hf1}};
  reg [7:0] RAM[(1<<16)-1:0];

endmodule