module Conditional(acc,op,carry,out);
  input [7:0] acc;
  input [2:0] op;
  input carry;
  output reg out;
  
  wire notZero;
  assign notZero = |acc;
  always @(*)
    case(op)
      3'h0:out = 1'h1;
      3'h1:out = notZero & !acc[7];
      3'h2:out = !acc[7];
      3'h3:out = !notZero;
      3'h4:out = acc[7];
      3'h5:out = !notZero | acc[7];
      3'h6:out = carry;
      3'h7:out = notZero;
    endcase;
endmodule