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S.. \.. i.. .. .. .. ./ // /'/ ,/9/ >/K/ %P/\/t///"//"0,0 >40D0K0 ]0 Eb0~0 0 E0H{HD$1C8D$H{HHHHHH{HH{HHHHC(HHߺ[]A\A]H{H[]A\A]HHHHf.@UHSHHHH{Ht HH HH[]H}pHI|$pHHHAGHH߉D$Dd$HHIEDHHxpHHD$HHxpH~H (p) P.8E JW p\g lv`  !   8%"- bAR[!m zr~ zy  hg W    )16B 2KPB"[ @`e,HH" # (H hidma_ll_resetJhidma_ll_set_transfer_params^ehidma_ll_enablehidma_handle_tre_completionhidma_ll_int_handler_internalhidma_post_completedhidma_ll_freeyhidma_request_msihidma_alloc_chan_resourcesohidma_pause:hidma_resumePhidma_terminate_channelhidma_probe?Othidma_removehidma_shutdownQCOM8061QCOM8062QCOM8063nr_desc_prmhidma_ll_chstats P(0 8< TD WP 8 T W8P 8 T W 8 T$ W@HP 8\ Td Wp 8 T W  8 T$ W`h0p 8| _ W(0 8 _ W  8 T W p(0 8< TD W`  I L   T L  z(0 < ID L` hPp | T L 2  T Lh  W$ L@HP \ Id L  W L   W L b  W$ L@ zHP \ Id L@@H P K\ hd k) ) tre_index [%d] and tre out of sync tre count mismatch on completiontransfer channel did not reset trying to free an unused TRE:%devent channel did not get enabled transfer channel did not get enabled HW reports invalid EVRE write offset invalid TRE number in transfer params:%dtrying to set params on an unused TRE:%doverriding number of descriptors as %d unable to set coherent mask to 64failed to request MSI irq, falling back to wired IRQ HI-DMA engine driver registration complete drivers/dma/qcom/../dmaengine.hinvalid TRE number in chstats:%d0D $(0d8@HTPXP`d h p xt    t$D4Dd$$` ("0$#8t$@%H'PD(X)`)h*p +x,//fe  invalid TRE number in free:%derror 0x%x, disabling... drivers/dma/qcom/hidma_ll.c3%s %s: 4HI-DMA engine shutdown channel did not stop HI-DMA engine removed failed to resume the channelchid%d drivers/dma/qcom/hidma.cdesc-countqcom-hidma-msiqcom-hidmaDMA enginechannel alloc failed at %u channel did not pause 4%s %s: 36hidmanr_descriptors=%d dev_trca=%p dev_trca_phys=%pa dev_trca_size=%pa dev_evca=%p dev_evca_phys=%pa dev_evca_size=%pa ------Channel %d ----- allocated=%d queued = 0x%x err_info = 0x%x err_code = 0x%x status = 0x%x idx = 0x%x dma_sig = 0x%x dev_name=%s callback=%p data=%p tre_index = 0x%x src=%pap dest=%pap length = 0x%x paused=%u dma_sig=%u prepared active completed ------Device ----- lldev init = 0x%x trch_state = 0x%x evch_state = 0x%x chidx = 0x%x nr_tres = 0x%x trca=%p tre_ring=%p tre_ring_handle=%pap tre_ring_size = 0x%x tre_processed_off = 0x%x pending_tre_count=%d evca=%p evre_ring=%p evre_ring_handle=%pap evre_ring_size = 0x%x evre_processed_off = 0x%x tre_write_offset = 0x%x chan%dstatsdrivers/dma/qcom/hidma_dbg.c3%s %s: license=GPL v2description=Qualcomm Technologies HIDMA Channel supportparm=nr_desc_prm:number of descriptors (default: 0)parmtype=nr_desc_prm:uint 0 ( ZX 0 (0P8@H@PX@`P h p x`    `0 0PppP" #(`$0%8'@0(H)P)X*`+h,p/x/@ ( 08@`H PX`@hpx@` @" 6 o#GCC: (GNU) 14.2.1 20240910GCC: (GNU) 14.2.1 20240910GCC: (GNU) 14.2.1 20240910 <l|<  F  P`p  )T :+X++L+X:Q:] u: : : : int ] ,: *:Ms8iMu8|XMs16Mu16+X+Ms32?Mu32XNMs64Mu64gXg].  : +  1] 2] H I X ] ^ _ `Q:: <]  N T    ) #: % & 4 = B h? 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